1. Field of the Invention
The present invention relates to a method of forming an isolating region of a semiconductor device and, more particularly to a method of forming the isolating region of a semiconductor device, for forming an isolating layer having no void in a trench, after the formation of the trench, that will provide a device isolating region for 1 Gb, and also provide for planarization of the device.
2. Discussion of Related Art
With the higher integration of a semiconductor device, there are suggested a variety of methods of forming an isolating region of the semiconductor device and a forming region, namely, an active region, in a smaller size. LOCOS (Local Oxidation of Silicon) is a prevailing technique used in forming an isolating region of a semiconductor device due to its simplicity and excellent reproductivity. It is known however that the LOCOS is not suitable for a DRAM of above 64 MB, because of the bird's beaking phenomenon, which is characteristic of an isolating region formed through LOCOS which occurs at the edge of the isolating oxide layer and is extended to the active region, wherein the active region is decreased. Therefore, an advanced LOCOS is employed in the fabrication of a DRAM with 64 MB or 256 MB, so as to reduce the isolating region but increase the active region by preventing the occurrence of the birds' beaking phenomenon or removing the bird's beaking phenomenon itself. But, this advanced LOCOS method still presents some problems of deterioration of the characteristic of the isolating region for a DRAM of above the 1 Gb level which requires a cell region to be 0.2 .mu.m.sup.2 in area. One of the above problems is the extremely large size of the isolating region and another problem is the leakage of current, which results from the formation of a field oxide layer in the interface with the silicon substrate through the LOCOS and thus a decreased concentration of the silicon substrate. For this reason, there is suggested a new method in forming the isolating region for a DRAM of above the 1 Gb level by using a trench having an easily regulated thickness for the purpose of promoting an isolating effect.
FIGS. 1a-1f are sectional views illustrating a conventional process for forming the isolating region of a semiconductor device.
As shown in FIG. 1a, a pad oxide layer 2 and a polysilicon layer 3 are sequentially formed on a substrate 1, and thereafter divided into patterns which vary in width and space by selective patterning through photolithography and etching. The substrate 1 is then etched to a predetermined depth using the divided polysilicon layer 3 and pad oxide layer 2 as masks so as to form trenches 4 which vary in width.
Referring to FIG. 1b, there is formed a thermal oxide layer 5 along the surface of the trenches 4, and a CVD (Chemical Vapor Deposition) oxide layer 6 is formed on the whole surface of the trench 4 by using an ECR (Electron-Cyclotron-Resonance) apparatus. According to the deposition of the CVD oxide layer 6 with the ECR apparatus, the oxide layer is formed from SiH.sub.4 /N.sub.2 O gas in an ECR plasma system.
In FIG. 1c, the CVD oxide layer 6 is laterally etched. As a result, the CVD oxide layer 6 formed in the trenches 4 are not etched, but the top edge of the polysilicon layer 3 is exposed, decreasing the width of the CVD oxide layer 6 formed thereon. Further, the CVD oxide layer 6 on the narrow polysilicon layer 3 is completely removed by lateral etching.
In FIG. 1d, after forming a photoresist PR on the whole surface of the polysilicon layer 3 and the CDV oxide layer 6, the CVD oxide layer 6 which was not etched can be selectively exposed by exposure and development. In this process, the top edge of the polysilicon layer 3 formed beneath the CVD oxide layer 6 is partially exposed.
Referring to FIG. 1e, the exposed CVD oxide layer 6 is selectively removed by using the photoresist PR as a mask, which is then also removed.
Finally, in FIG. 1f, the polysilicon layer 3 and the pad oxide layer 2 are removed in sequence as the last step of the conventional process for forming the isolating layer of a semiconductor device.
The problems of the conventional method of forming the isolating layer may be summarized as follows.
First, the process is too complicated. After the CVD oxide layer is formed in the trenches, the process for removing the CVD oxide layer on the polysilicon layer other than the trenches requires lateral etching and patterning, using a photoresist as a mask through photolithography and etching.
Second, if the CVD oxide layer formed in the trench is higher than the upper surface of the polysilicon layer in the deposition of the CVD oxide layer so as to bury the trench, a lateral etching is required for the removal of the CVD oxide layer, and further the CVD oxide layer on the edge of the polysilicon layer is incompletely removed because the edge of the polysilicon layer is masked by the photoresist. The edge of the polysilicon layer is therefore masked by the CVD oxide layer which was incompletely removed, and thus the polysilicon layer beneath the CVD oxide layer may not be etched out during the removal of the polysilicon layer. For this reason, an additional process is required to completely remove the CVD oxide layer and the polysilicon layer beneath the CVD oxide layer, which leads to a reduction in productivity and an increase in production cost.